View MC145484_1378130.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MC145484 motorola 1 advance information the MC145484 is a general purpose per channel pcm codecfilter with pin selectable mulaw or alaw companding, and is offered in 20pin sog and ssop packages. this device performs the voice digitization and reconstruction as well as the band limiting and smoothing required for pcm systems. this device is designed to operate in both synchronous and asynchronous applications and contains an onchip precision reference voltage. this device has an input operational amplifier whose output is the input to the encoder section. the encoder section immediately lowpass filters the analog signal with an active rc filter to eliminate very high frequency noise from being modulated down to the passband by the switched capacitor filter. from the active rc filter, the analog signal is converted to a differential signal. from this point, all analog signal processing is done differentially. this allows processing of an analog signal that is twice the amplitude allowed by a singleended design, which reduces the significance of noise to both the inverted and noninverted signal paths. another advantage of this differential design is that noise injected via the power supplies is a commonmode signal that is cancelled when the inverted and noninverted signals are recombined. this dramatically improves the power supply rejection ratio. after the differential converter, a differential switched capacitor filter band passes the analog signal from 200 hz to 3400 hz before the signal is digitized by the differential compressing a/d converter. the decoder accepts pcm data and expands it using a differential d/a converter. the output of the d/a is lowpass filtered at 3400 hz and sinx/x compensated by a differential switched capacitor filter. the signal is then filtered by an active rc filter to eliminate the outofband energy of the switched capacitor filter. the MC145484 pcm codecfilter has a high impedance v ag reference pin which allows for decoupling of the internal circuitry that generates the midsupply v ag reference voltage, to the v ss power supply ground. this reduces clock noise on the analog circuitry when external analog signals are referenced to the power supply ground. this device is optimal for electronic slic interfaces. the MC145484 pcm codecfilter accepts a variety of clock formats, including short frame sync, long frame sync, idl, and gci timing environments. this device also maintains compatibility with motorola's family of telecommunication products, including the mc14lc5472 and mc145572 uinterface transceivers, mc145474/75 and mc145574 s/tinterface trans- ceivers, mc145532 adpcm transcoder, mc145422/26 udlt1, mc145421/25 udlt2, and mc3419/mc33120 slics. the MC145484 pcm codecfilter utilizes cmos due to its reliable lowpower performance and proven capability for complex analog/digital vlsi functions. ? single 5 v power supply ? typical power dissipation of 15 mw, powerdown of 0.01 mw ? fullydifferential analog circuit design for lowest noise ? transmit bandpass and receive lowpass filters onchip ? active rc prefiltering and postfiltering ? mulaw and alaw companding by pin selection ? onchip precision reference voltage of 1.575 v for a 0 dbm tlp @ 600 w ? pushpull 300 w power drivers with external gain adjust ? mc14lc5480evk is the evaluation kit for this device this document contains information on a new product. specifications and information herein are subject to change without notice. order this document by MC145484/d
semiconductor technical data pin assignment dw suffix sog package case 751d ordering information MC145484dw sog package MC145484sd ssop 20 1 v dd po pi ro v ag ref pdi bclkr dr fsr po+ 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 mu/a tg ti ti+ v ag mclk bclkt dt fst v ss sd suffix ssop case 940c 20 1 ? motorola, inc. 1997 rev 0 2/97 tn97022700
MC145484 motorola 2 freq freq ro pi po po + v dd v ss v ag tg ti ti + + 1 1 + shared dac dac 1.575 v ref adc transmit shift register sequence and control dr fsr bclkr mu/a pdi mclk bclkt fst dt receive shift register v ag ref v dd v ss r* r* figure 1. MC145484 5 v pcm codecfilter block diagram device description a pcm codecfilter is used for digitizing and reconstruct- ing the human voice. these devices are used primarily for the telephone network to facilitate voice switching and trans- mission. once the voice is digitized, it may be switched by digital switching methods or transmitted long distance (t1, microwave, satellites, etc.) without degradation. the name codec is an acronym from ``coder'' for the analogtodigital converter (adc) used to digitize voice, and ``decoder'' for the digitaltoanalog converter (dac) used for reconstruct- ing voice. a codec is a single device that does both the adc and dac conversions. to digitize intelligible voice requires a signaltodistortion ratio of about 30 db over a dynamic range of about 40 db. this may be accomplished with a linear 13bit adc and dac, but will far exceed the required signaltodistortion ratio at larger amplitudes than 40 db below the peak ampli- tude. this excess performance is at the expense of data per sample. two methods of data reduction are implemented by compressing the 13bit linear scheme to companded pseudologarithmic 8bit schemes. the two companding schemes are: mu255 law, primarily in north america and japan; and alaw, primarily used in europe. these com- panding schemes are accepted world wide. these compand- ing schemes follow a segmented or ``piecewiselinear'' curve formatted as sign bit, three chord bits, and four step bits. for a given chord, all sixteen of the steps have the same voltage weighting. as the voltage of the analog input increases, the four step bits increment and carry to the three chord bits which increment. when the chord bits increment, the step bits double their voltage weighting. this results in an effec- tive resolution of six bits (sign + chord + four step bits) across a 42 db dynamic range (seven chords above 0, by 6 db per chord). in a sampling environment, nyquist theory says that to properly sample a continuous signal, it must be sampled at a frequency higher than twice the signal's highest frequency component. voice contains spectral energy above 3 khz, but its absence is not detrimental to intelligibility. to reduce the digital data rate, which is proportional to the sampling rate, a sample rate of 8 khz was adopted, consistent with a band- width of 3 khz. this sampling requires a lowpass filter to limit the high frequency energy above 3 khz from distorting the inband signal. the telephone line is also subject to 50/60 hz power line coupling, which must be attenuated from the signal by a highpass filter before the analogto digital converter. the digitaltoanalog conversion process reconstructs a staircase version of the desired inband signal, which has spectral images of the inband signal modulated about the sample frequency and its harmonics. these spectral images are called aliasing components, which need to be attenuated to obtain the desired signal. the lowpass filter used to at- tenuate these aliasing components is typically called a re- construction or smoothing filter. the MC145484 pcm codecfilter has the codec, both presampling and reconstruction filters, and a precision volt- age reference onchip.
MC145484 motorola 3 pin descriptions power supply v dd positive power supply (pin 6) this is the most positive power supply and is typically con- nected to + 5 v. this pin should be decoupled to v ss with a 0.1 m f ceramic capacitor. v ss negative power supply (pin 15) this is the most negative power supply and is typically connected to 0 v. v ag analog ground output (pin 20) this output pin provides a midsupply analog ground. this pin should be decoupled to v ss with a 0.01 m f ceramic ca- pacitor. all analog signal processing within this device is ref- erenced to this pin. if the audio signals to be processed are referenced to v ss , then special precautions must be utilized to avoid noise between v ss and the v ag pin. refer to the ap- plications information in this document for more information. the v ag pin becomes high impedance when this device is in the powereddown mode. v ag ref analog ground reference bypass (pin 1) this pin is used to capacitively bypass the onchip circuit- ry that generates the midsupply voltage for the v ag output pin. this pin should be bypassed to v ss with a 0.1 m f ceram- ic capacitor using short, low inductance traces. the v ag ref pin is only used for generating the reference voltage for the v ag pin. nothing is to be connected to this pin in addition to the bypass capacitor. all analog signal processing within this device is referenced to the v ag pin. if the audio signals to be processed are referenced to v ss , then special precautions must be utilized to avoid noise between v ss and the v ag pin. refer to the applications information in this document for more information. when this device is in the powereddown mode, the v ag ref pin is pulled to the v dd power supply with a nonlinear, highimpedance circuit. control mu/a mu/a law select (pin 16) this pin controls the compression for the encoder and the expansion for the decoder. mulaw companding is selected when this pin is connected to v dd and alaw companding is selected when this pin is connected to v ss . pdi powerdown input (pin 10) this pin puts the device into a low power dissipation mode when a logic 0 is applied. when this device is powered down, all of the clocks are gated off and all bias currents are turned off, which causes ro, po, po+, tg, v ag , and dt to be- come high impedance and the v ag ref pin is pulled to the v dd power supply with a nonlinear, highimpedance circuit. the device will operate normally when a logic 1 is applied to this pin. the device goes through a powerup sequence when this pin is taken to a logic 1 state, which prevents the dt pcm output from going low impedance for at least two fst cycles. the v ag and v ag ref circuits and the signal pro- cessing filters must settle out before the dt pcm output or the ro receive analog output will represent a valid analog signal. analog interface ti+ transmit analog input (noninverting) (pin 19) this is the noninverting input of the transmit input gain setting operational amplifier. this pin accommodates a differ- ential to singleended circuit for the input gain setting op amp. this allows input signals that are referenced to the v ss pin to be level shifted to the v ag pin with minimum noise. this pin may be connected to the v ag pin for an inverting amplifier configuration if the input signal is already refer- enced to the v ag pin. the common mode range of the ti+ and ti pins is from 1.2 v, to v dd minus 1.2 v. this is an fet gate input. the ti+ pin also serves as a digital input control for the transmit input multiplexer. connecting the ti+ pin to v dd will place this amplifier's output (tg) into a highimpedance state, and selects the tg pin to serve as a highimpedance input to the transmit filter. connecting the ti+ pin to v ss will also place this amplifier's output (tg) into a highimpedance state, and selects the ti pin to serve as a highimpedance input to the transmit filter. ti transmit analog input (inverting) (pin 18) this is the inverting input of the transmit gain setting op- erational amplifier. gain setting resistors are usually con- nected from this pin to tg and from this pin to the analog signal source. the common mode range of the ti+ and ti pins is from 1.2 v to v dd 1.2 v. this is an fet gate input. the ti pin also serves as one of the transmit input multi- plexer pins when the ti+ pin is connected to v ss . when ti+ is connected to v dd , this pin is ignored. see the pin descrip- tions for the ti+ and the tg pins for more information. tg transmit gain (pin 17) this is the output of the transmit gain setting operational amplifier and the input to the transmit bandpass filter. this op amp is capable of driving a 2 k w load. connecting the ti+ pin to v dd will place the tg pin into a highimpedance state, and selects the tg pin to serve as a highimpedance input to the transmit filter. all signals at this pin are referenced to the v ag pin. when ti+ is connected to v ss , this pin is ignored. see the pin descriptions for the ti+ and ti pins for more in- formation. this pin is high impedance when the device is in the powereddown mode.
MC145484 motorola 4 ro receive analog output (inverting) (pin 2) this is the inverting output of the receive smoothing filter from the digitaltoanalog converter. this output is capable of driving a 2 k w load to 1.575 v peak referenced to the v ag pin. if the device is operated halfchannel with the fst pin clocking and fsr pin held low, the receive filter input will be conencted to the v ag voltage. this minimizes transients at the ro pin when fullchannel operation is resumed by clocking the fsr pin. this pin is high impedance when the device is in the powereddown mode. pi power amplifier input (pin 3) this is the inverting input to the po amplifier. the non inverting input to the po amplifier is internally tied to the v ag pin. the pi and po pins are used with external resis- tors in an inverting op amp gain circuit to set the gain of the po+ and po pushpull power amplifier outputs. connect- ing pi to v dd will power down the power driver amplifiers and the po+ and po outputs will be high impedance. po power amplifier output (inverting) (pin 4) this is the inverting power amplifier output, which is used to provide a feedback signal to the pi pin to set the gain of the pushpull power amplifier outputs. this pin is capable of driving a 300 w load to po+. the po+ and po outputs are differential (pushpull) and capable of driving a 300 w load to 3.15 v peak, which is 6.3 v peaktopeak. the bias voltage and signal reference of this output is the v ag pin. the v ag pin cannot source or sink as much current as this pin, and therefore low impedance loads must be between po+ and po. the po+ and po differential drivers are also capable of driving a 100 w resistive load or a 100 nf piezoelectric transducer in series with a 20 w resister with a small increase in distortion. these drivers may be used to drive resistive loads of 32 w when the gain of po is set to 1/4 or less. connecting pi to v dd will power down the power driver am- plifiers and the po+ and po outputs will be high imped- ance. this pin is also high impedance when the device is powered down by the pdi pin. po+ power amplifier output (noninverting) (pin 5) this is the noninverting power amplifier output, which is an inverted version of the signal at po. this pin is capable of driving a 300 w load to po. connecting pi to v dd will power down the power driver amplifiers and the po+ and po outputs will be high impedance. this pin is also high im- pedance when the device is powered down by the pdi pin. see pi and po for more information. digital interface mclk master clock (pin 11) this is the master clock input pin. the clock signal applied to this pin is used to generate the internal 256 khz clock and sequencing signals for the switchedcapacitor filters, adc, and dac. the internal prescaler logic compares the clock on this pin to the clock at fst (8 khz) and will automatically accept 256, 512, 1536, 1544, 2048, 2560, or 4096 khz. for mclk frequencies of 256 and 512 khz, mclk must be syn- chronous and approximately rising edge aligned to fst. for optimum performance at frequencies of 1.536 mhz and higher, mclk should be synchronous and approximately ris- ing edge aligned to the rising edge of fst. in many ap- plications, mclk may be tied to the bclkt pin. fst frame sync, transmit (pin 14) this pin accepts an 8 khz clock that synchronizes the out- put of the serial pcm data at the dt pin. this input is com- patible with various standards including idl, long frame sync, short frame sync, and gci formats. if both fst and fsr are held low for several 8 khz frames, the device will power down. bclkt bit clock, transmit (pin 12) this pin controls the transfer rate of transmit pcm data. in the idl and gci modes it also controls the transfer rate of the receive pcm data. this pin can accept any bit clock fre- quency from 64 to 4096 khz for long frame sync and short frame sync timing. this pin can accept clock frequencies from 256 khz to 4.096 mhz in idl mode, and from 512 khz to 6.176 mhz for gci timing mode. dt data, transmit (pin 13) this pin is controlled by fst and bclkt and is high im- pedance except when outputting pcm data. when operating in the idl or gci mode, data is output in either the b1 or b2 channel as selected by fsr. this pin is high impedance when the device is in the powered down mode. fsr frame sync, receive (pin 7) when used in the long frame sync or short frame sync mode, this pin accepts an 8 khz clock, which synchronizes the input of the serial pcm data at the dr pin. fsr can be asynchronous to fst in the long frame sync or short frame sync modes. when an isdn mode (idl or gci) has been selected with bclkr, this pin selects either b1 (logic 0) or b2 (logic 1) as the active data channel. bclkr bit clock, receive (pin 9) when used in the long frame sync or short frame sync mode, this pin accepts any bit clock frequency from 64 to 4096 khz. when this pin is held at a logic 1, fst, bclkt, dt, and dr become idl interface compatible. when this pin is held at a logic 0, fst, bclkt, dt, and dr become gci inter- face compatible. dr data, receive (pin 8) this pin is the pcm data input, and when in a long frame sync or short frame sync mode is controlled by fsr and bclkr. when in the idl or gci mode, this data transfer is controlled by fst and bclkt. fsr and bclkr select the b channel and isdn mode, respectively.
MC145484 motorola 5 functional description analog interface and signal path the transmit portion of this device includes a lownoise, threeterminal op amp capable of driving a 2 k w load. this op amp has inputs of ti+ (pin 19) and ti (pin 18) and its output is tg (pin 17). this op amp is intended to be confi- gured in an inverting gain circuit. the analog signal may be applied directly to the tg pin if this transmit op amp is inde- pendently powered down by connecting the ti+ input to the v dd power supply. the tg pin becomes high impedance when the transmit op amp is powered down. the tg pin is internally connected to a 3pole antialiasing prefilter. this prefilter incorporates a 2pole butterworth active lowpass filter, followed by a single passive pole. this prefilter is fol- lowed by a singleended to differential converter that is clocked at 512 khz. all subsequent analog processing uti- lizes fullydifferential circuitry. the next section is a fullydif- ferential, 5pole switchedcapacitor lowpass filter with a 3.4 khz frequency cutoff. after this filter is a 3pole switchedcapacitor highpass filter having a cutoff fre- quency of about 200 hz. this highpass stage has a trans- mission zero at dc that eliminates any dc coming from the analog input or from accumulated op amp offsets in the pre- ceding filter stages. the last stage of the highpass filter is an autozeroed sample and hold amplifier. one bandgap voltage reference generator and digitalto analog converter (dac) are shared by the transmit and re- ceive sections. the autozeroed, switchedcapacitor bandgap reference generates precise positive and negative reference voltages that are virtually independent of tempera- ture and power supply voltage. a binaryweighted capacitor array (cdac) forms the chords of the companding structure, while a resistor string (rdac) implements the linear steps within each chord. the encode process uses the dac, the voltage reference, and a framebyframe autozeroed comparator to implement a successiveapproximation con- version algorithm. all of the analog circuitry involved in the data conversion (the voltage reference, rdac, cdac, and comparator) are implemented with a differential architecture. the receive section includes the dac described above, a sample and hold amplifier, a 5pole, 3400 hz switched ca- pacitor lowpass filter with sinx/x correction, and a 2pole active smoothing filter to reduce the spectral components of the switched capacitor filter. the output of the smoothing fil- ter is buffered by an amplifier, which is output at the ro pin. this output is capable of driving a 2 k w load to the v ag pin. the MC145484 also has a pair of power amplifiers that are connected in a pushpull configuration. the pi pin is the in- verting input to the po power amplifier. the noninverting input is internally tied to the v ag pin. this allows this amplifier to be used in an inverting gain circuit with two external resis- tors. the po+ a mplifier has a gain of minus one, and is in- ternally connected to the po output. this complete power amplifier circuit is a differential (pushpull) amplifier with ad- justable gain that is capable of driving a 300 w load to + 12 dbm. the power amplifier may be powered down inde- pendently of the rest of the chip by connecting the pi pin to v dd . powerdown there are two methods of putting this device into a low power consumption mode, which makes the device nonfunc- tional and consumes virtually no power. pdi is the power down input pin which, when taken low, powers down the device. another way to power the device down is to hold both the fst and fsr pins low while the bclkt and mclk pins are clocked. when the chip is powered down, the v ag , tg, ro, po+, po, and dt outputs are high impedance and the v ag ref pin is pulled to the v dd power supply with a non linear, highimpedance circuit. to return the chip to the pow- erup state, pdi must be high and the fst frame sync pulse must be present while the bclkt and mclk pins are clocked. the dt output will remain in a highimpedance state for at least two 8 khz fst pulses after powerup. master clock since this codecfilter design has a single dac architec- ture, the mclk pin is used as the master clock for all analog signal processing including analogtodigital conversion, digitaltoanalog conversion, and for transmit and receive fil- tering functions of this device. the clock frequency applied to the mclk pin may be 256 khz, 512 khz, 1.536 mhz, 1.544 mhz, 2.048 mhz, 2.56 mhz, or 4.096 mhz. this de- vice has a prescaler that automatically determines the proper divide ratio to use for the mclk input, which achieves the re- quired 256 khz internal sequencing clock. the clocking re- quirements of the mclk input are independent of the pcm data transfer mode (i.e., long frame sync, short frame sync, idl mode, or gci mode). digital i/o the MC145484 is pin selectable for mulaw or alaw. table 1 shows the 8bit data word format for positive and negative zero and full scale for both companding schemes. table 2 shows the series of eight pcm words for both mu law and alaw that correspond to a digital milliwatt. the digital mw is the 1 khz calibration signal reconstructed by the dac that defines the absolute gain or 0 dbm0 transmis- sion level point (tlp) of the dac. the timing for the pcm data transfer is independent of the companding scheme se- lected. refer to figure 2 for a summary and comparison of the four pcm data interface modes of this device.
MC145484 motorola 6 table 1. pcm codes for zero and full scale ll mulaw alaw level sign bit chord bits step bits sign bit chord bits step bits + full scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 + zero 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 zero 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 full scale 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 table 2. pcm codes for digital mw ph mulaw alaw phase sign bit chord bits step bits sign bit chord bits step bits p /8 0 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 3 p /8 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 5 p /8 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 7 p /8 0 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 9 p /8 1 0 0 1 1 1 1 0 1 0 1 1 0 1 0 0 11 p /8 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 13 p /8 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 15 p /8 1 0 0 1 1 1 1 0 1 0 1 1 0 1 0 0
MC145484 motorola 7 figure 2a. long frame sync (transmit and receive have individual clocking) figure 2b. short frame sync (transmit and receive have individual clocking) figure 2c. idl interface e bclkr = 1 (transmit and receive have common clocking) figure 2d. gci interface e bclkr = 0 (transmit and receive have common clocking) d in (dr) idl rx (dr) don't care don't care 8 dr 8 7 6 5 4 3 2 1 dr don't care don't care 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 b2channel (fsr = 1) b1channel (fsr = 0) b2channel (fsr = 1) b1channel (fsr = 0) d out (dt) dcl (bclkt) fsc (fst) idl tx (dt) idl clock (bclkt) idl sync (fst) dt bclkt (bclkr) fst (fsr) dt bclkt (bclkr) fst (fsr) don't care don't care don't care don't care don't care 7 6 5 4 3 2 1 8 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 figure 2. digital timing modes for the pcm data interface
MC145484 motorola 8 long frame sync long frame sync is the industry name for one type of clocking format that controls the transfer of the pcm data words. (refer to figure 2a.) the ``frame sync'' or ``enable'' is used for two specific synchronizing functions. the first is to synchronize the pcm data word transfer, and the second is to control the internal analogtodigital and digitaltoanalog conversions. the term ``sync'' refers to the function of syn- chronizing the pcm data word onto or off of the multiplexed serial pcm data bus, which is also known as a pcm high- way. the term ``long'' comes from the duration of the frame sync measured in pcm data clock cycles. long frame sync timing occurs when the frame sync is used directly as the pcm data output driver enable. this results in the pcm out- put going low impedance with the rising edge of the transmit frame sync, and remaining low impedance for the duration of the transmit frame sync. the implementation of long frame sync has maintained compatibility and been optimized for external clocking sim- plicity. this optimization includes the pcm data output going low impedance with the logical and of the transmit frame sync (fst) with the transmit data bit clock (bclkt). the op- timization also includes the pcm data output (dt) remaining low impedance until the middle of the lsb (seven and a half pcm data clock cycles) or until the fst pin is taken low, whichever occurs last. this requires the frame sync to be approximately rising edge aligned with the initiation of the pcm data word transfer, but the frame sync does not have a precise timing requirement for the end of the pcm data word transfer. the device recognizes long frame sync clocking when the frame sync is held high for two consecutive falling edges of the transmit data clock. the transmit logic decides on each frame sync whether it should interpret the next frame sync pulse as a long or a short frame sync. this de- cision is used for receive circuitry also. the device is de- signed to prevent pcm bus contention by not allowing the pcm data output to go low impedance for at least two frame sync cycles after power is applied or when coming out of the powered down mode. the receive side of the device is designed to accept the same frame sync and data clock as the transmit side and to be able to latch its own transmit pcm data word. thus the pcm digital switch needs to be able to generate only one type of frame sync for use by both transmit and receive sec- tions of the device. the logical and of the receive frame sync with the receive data clock tells the device to start latching the 8bit serial word into the receive data input on the falling edges of the receive data clock. the internal receive logic counts the re- ceive data clock cycles and transfers the pcm data word to the digitaltoanalog converter sequencer on the ninth data clock rising edge. this device is compatible with four digital interface modes. to ensure that this device does not reprogram itself for a dif- ferent timing mode, the bclkr pin must change logic state no less than every 125 m s. the minimum pcm data bit clock frequency of 64 khz satisfies this requirement. short frame sync short frame sync is the industry name for the type of clocking format that controls the transfer of the pcm data words (refer to figure 2b). the ``frame sync'' or ``enable'' is used for two specific synchronizing functions. the first is to synchronize the pcm data word transfer, and the second is to control the internal analogtodigital and digitaltoanalog conversions. the term ``sync'' refers to the function of syn- chronizing the pcm data word onto or off of the multiplexed serial pcm data bus, which is also known as a pcm high- way. the term ``short'' comes from the duration of the frame sync measured in pcm data clock cycles. short frame sync timing occurs when the frame sync is used as a ``presyn- chronization'' pulse that is used to tell the internal logic to clock out the pcm data word under complete control of the data clock. the short frame sync is held high for one falling data clock edge. the device outputs the pcm data word be- ginning with the following rising edge of the data clock. this results in the pcm output going low impedance with the ris- ing edge of the transmit data clock, and remaining low im- pedance until the middle of the lsb (seven and a half pcm data clock cycles). the device recognizes short frame sync clocking when the frame sync is held high for one and only one falling edge of the transmit data clock. the transmit logic decides on each frame sync whether it should interpret the next frame sync pulse as a long or a short frame sync. this decision is used for receive circuitry also. the device is designed to prevent pcm bus contention by not allowing the pcm data output to go low impedance for at least two frame sync cycles after power is applied or when coming out of the powered down mode. the receive side of the device is designed to accept the same frame sync and data clock as the transmit side and to be able to latch its own transmit pcm data word. thus the pcm digital switch needs to be able to generate only one type of frame sync for use by both transmit and receive sec- tions of the device. the falling edge of the receive data clock latching a high logic level at the receive frame sync input tells the device to start latching the 8bit serial word into the receive data input on the following eight falling edges of the receive data clock. the internal receive logic counts the receive data clock cycles and transfers the pcm data word to the digitalto analog converter sequencer on the rising data clock edge af- ter the lsb has been latched into the device. this device is compatible with four digital interface modes. to ensure that this device does not reprogram itself for a dif- ferent timing mode, the bclkr pin must change logic state no less than every 125 m s. the minimum pcm data bit clock frequency of 64 khz satisfies this requirement. interchip digital link (idl) the interchip digital link (idl) interface is one of two standard synchronous 2b+d isdn timing interface modes with which this device is compatible. in the idl mode, the de- vice can communicate in either of the two 64 kbps b chan- nels (refer to figure 2c for sample timing). the idl mode is selected when the bclkr pin is held high for two or more fst (idl sync) rising edges. the digital pins that control the transmit and receive pcm word transfers are repro- grammed to accommodate this mode. the pins affected are fst, fsr, bclkt, dt, and dr. the idl interface consists of four pins: idl sync (fst), idl clk (bclkt), idl tx (dt), and idl rx (dr). the idl interface mode provides access to both the transmit and receive pcm data words with common control clocks of idl sync and idl clock. in this mode, the
MC145484 motorola 9 fsr pin controls whether the b1 channel or the b2 channel is used for both transmit and receive pcm data word trans- fers. when the fsr pin is low, the transmit and receive pcm words are transferred in the b1 channel, and for fsr high the b2 channel is selected. the start of the b2 channel is ten idl clk cycles after the start of the b1 channel. the idl sync (fst, pin 14) is the input for the idl frame synchronization signal. the signal at this pin is nominally high for one cycle of the idl clock signal and is rising edge aligned with the idl clock signal. (refer to figure 4 and the idl timing specifications for more details.) this event identi- fies the beginning of the idl frame. the frequency of the idl sync signal is 8 khz. the rising edge of the idl sync (fst) should be aligned approximately with the rising edge of mclk. mclk must be one of the clock frequencies specified in the digital switching characteristics table, and is typically tied to idl clk (bclkt). the idl clk (bclkt, pin 12) is the input for the pcm data clock. all idl pcm transfers and data control sequenc- ing are controlled by this clock following the idl sync. this pin accepts an idl data clock frequency of 256 khz to 4.096 mhz. the idl tx (dt, pin 13) is the output for the transmit pcm data word. data bits are output for the b1 channel on se- quential rising edges of the idl clk signal beginning after the idl sync pulse. if the b2 channel is selected, then the pcm word transfer starts on the eleventh idl clk rising edge after the idl sync pulse. the idl tx pin will remain low impedance for the duration of the pcm word until the lsb after the falling edge of idl clk. the idl tx pin will re- main in a high impedance state when not outputting pcm data or when a valid idl sync signal is missing. the idl rx (dr, pin 8) is the input for the receive pcm data word. data bits are input for the b1 channel on sequen- tial falling edges of the idl clk signal beginning after the idl sync pulse. if the b2 channel is selected, then the pcm word is latched in starting on the eleventh idl clk falling edge after the idl sync pulse. general circuit interface (gci) the general circuit interface (gci) is the second of two standard synchronous 2b+d isdn timing interface modes with which this device is compatible. in the gci mode, the device can communicate in either of the two 64 kbps b channels. (refer to figure 2d for sample timing.) the gci mode is selected when the bclkr pin is held low for two or more fst (fsc) rising edges. the digital pins that control the transmit and receive pcm word transfers are repro- grammed to accommodate this mode. the pins affected are fst, fsr, bclkt, dt, and dr. the gci interface consists of four pins: fsc (fst), dcl (bclkt), d out (dt), and d in (dr). the gci interface mode provides access to both the transmit and receive pcm data words with common control clocks of fsc (frame synchronization clock) and dcl (data clock). in this mode, the fsr pin controls whether the b1 channel or the b2 channel is used for both transmit and re- ceive pcm data word transfers. when the fsr pin is low, the transmit and receive pcm words are transferred in the b1 channel, and for fsr high the b2 channel is selected. the start of the b2 channel is 16 dcl cycles after the start of the b1 channel. the fsc (fst, pin 14) is the input for the gci frame syn- chronization signal. the signal at this pin is nominally rising edge aligned with the dcl clock signal. (refer to figure 6 and the gci timing specifications for more details.) this event identifies the beginning of the gci frame. the frequen- cy of the fsc synchronization signal is 8 khz. the rising edge of the fsc (fst) should be aligned approximately with the rising edge of mclk. mclk must be one of the clock fre- quencies specified in the digital switching characteristics table, and is typically tied to dcl (bclkt). the dcl (bclkt, pin 12) is the input for the clock that controls the pcm data transfers. the clock applied at the dcl input is twice the actual pcm data rate. the gci frame begins with the logical and of the fsc with the dcl. this event initiates the pcm data word transfers for both transmit and receive. this pin accepts a gci data clock frequency of 512 khz to 6.176 mhz for pcm data rates of 256 khz to 3.088 mhz. the gci d out (dt, pin 13) is the output for the transmit pcm data word. data bits are output for the b1 channel on alternate rising edges of the dcl clock signal, beginning with the fsc pulse. if the b2 channel is selected, then the pcm word transfer starts on the seventeenth dcl rising edge after the fsc rising edge. the d out pin will remain low impedance for 151/2 dcl clock cycles. the d out pin becomes high impedance after the second falling edge of the dcl clock during the lsb of the pcm word. the d out pin will remain in a highimpedance state when not outputting pcm data or when a valid fsc signal is missing. the d in (dr, pin 8) is the input for the receive pcm data word. data bits are latched in for the b1 channel on alternate rising edges of the dcl clock signal, beginning with the se- cond dcl clock after the rising edge of the fsc pulse. if the b2 channel is selected then the pcm word is latched in start- ing on the eighteenth dcl rising edge after the fsc rising edge. printed circuit board layout considerations the MC145484 is manufactured using highspeed cmos vlsi technology to implement the complex analog signal processing functions of a pcm codecfilter. the fullydiffer- ential analog circuit design techniques used for this device result in superior performance for the switched capacitor fil- ters, the analogtodigital converter (adc) and the digital toanalog converter (dac). special attention was given to the design of this device to reduce the sensitivities of noise, including power supply rejection and susceptibility to radio frequency noise. this special attention to design includes a fifth order lowpass filter, followed by a third order highpass filter whose output is converted to a digital signal with greater than 75 db of dynamic range, all operating on a single 5 v power supply. this results in an lsb size for small audio sig- nals of about 386 m v. the typical idle channel noise level of this device is less than one lsb. in addition to the dynamic range of the codecfilter function of this device, the input gainsetting op amp has the capability of greater than 35 db of gain intended for an electret microphone interface. this device was designed for ease of implementation, but due to the large dynamic range and the noisy nature of the environment for this device (digital switches, radio tele-
MC145484 motorola 10 phones, dsp frontend, etc.) special care must be taken to assure optimum analog transmission performance. pc board mounting it is recommended that the device be soldered to the pc board for optimum noise performance. if the device is to be used in a socket, it should be placed in a low parasitic pin inductance (generally, lowprofile) socket. power supply, ground, and noise considerations this device is intended to be used in switching applica- tions which often require plugging the pc board into a rack with power applied. this is known as ``hotrack insertion.'' in these applications care should be taken to limit the voltage on any pin from going positive of the v dd pins, or negative of the v ss pins. one method is to extend the ground and power contacts of the pcb connector. the device has input protec- tion on all pins and may source or sink a limited amount of current without damage. current limiting may be accom- plished by series resistors between the signal pins and the connector contacts. the most important considerations for pcb layout deal with noise. this includes noise on the power supply, noise generated by the digital circuitry on the device, and cross coupling digital or radio frequency signals into the audio sig- nals of this device. the best way to prevent noise is to: 1. keep digital signals as far away from audio signals as possible. 2. keep radio frequency signals as far away from the audio signals as possible. 3. use short, low inductance traces for the audio circuitry to reduce inductive, capacitive, and radio frequency noise sensitivities. 4. use short, low inductance traces for digital and rf circuitry to reduce inductive, capacitive, and radio frequency radiated noise. 5. bypass capacitors should be connected from the v dd , v ag ref, and v ag pins to v ss with minimal trace length. ceramic monolithic capacitors of about 0.1 m f are acceptable for the v dd and v ag ref pins to decouple the device from its own noise. the v dd capacitor helps supply the instantaneous currents of the digital circuitry in addition to decoupling the noise which may be generated by other sections of the device or other circuitry on the power supply. the v ag ref decoupling capacitor is effecting a lowpass filter to isolate the midsupply voltage from the power supply noise gener- ated onchip as well as external to the device. the v ag decoupling capacitor should be about 0.01 m f. this helps to reduce the inpedance of the v ag pin to v ss at frequencies above the bandwidth of the v ag generator, which reduces the susceptibility to rf noise. 6. use a short, wide, low inductance trace to connect the v ss ground pin to the power supply ground. the v ss pin is the digital ground and the most negative power supply pin for the analog circuitry. all analog signal processing is referenced to the v ag pin, but because digital and rf circuitry will probably be powered by this same ground, care must be taken to minimize high frequency noise in the v ss trace. depending on the application, a double sided pcb with a v ss ground plane connecting all of the digital and analog v ss pins together would be a good grounding method. a multilayer pc board with a ground plane connecting all of the digital and analog v ss pins together would be the optimal ground configuration. these methods will result in the lowest resistance and the lowest inductance in the ground circuit. this is important to reduce voltage spikes in the ground circuit resulting from the high speed digital current spikes. the magnitude of digitally induced voltage spikes may be hundreds of times larger than the analog signal the device is required to digitize. 7. use a short, wide, low inductance trace to connect the v dd power supply pin to the 5 v power supply. depending on the application, a doublesided pcb with v dd bypass capacitors to the v ss ground plane, as described above, may complete the low impedance coupling for the power supply. for a multilayer pc board with a power plane, connecting all of the v dd pins to the power plane would be the optimal power distribution method. the integrated circuit layout and packaging considerations for the 5 v v dd power circuit are essentially the same as for the v ss ground circuit. 8. the v ag pin is the reference for all analog signal processing. in some applications the audio signal to be digitized may be referenced to the v ss ground. to reduce the susceptibility to noise at the input of the adc section, the threeterminal op amp may be used in a differential to singleended circuit to provide level conversion from the v ss ground to the v ag ground with noise cancellation. the op amp may be used for more than 35 db of gain in microphone interface circuits, which will require a compact layout with minimum trace lengths as well as isolation from noise sources. it is recom- mended that the layout be as symmetrical as possible to avoid any imbalances which would reduce the noise cancelling benefits of this differential op amp circuit. refer to the application schematics for examples of this circuitry. if possible, reference audio signals to the v ag pin instead of to the v ss pin. handset receivers and tele- phone line interface circuits using transformers may be audio signal referenced completely to the v ag pin. re- fer to the application schematics for examples of this circuitry. the v ag pin cannot be used for esd or line protection.
MC145484 motorola 11 maximum ratings (voltages referenced to v ss pin) rating symbol value unit dc supply voltage v dd 0.5 to 6 v voltage on any analog input or output pin v ss 0.3 to v dd + 0.3 v voltage on any digital input or output pin v ss 0.3 to v dd + 0.3 v operating temperature range t a 40 to + 85 c storage temperature range t stg 85 to +150 c power supply (t a = 40 to + 85 c) characteristics min typ max unit dc supply voltage 4.5 5.0 5.5 v active power dissipation (v dd = 5 v) (no load, pi v dd 0.5 v) (no load, pi v dd 1.5 v) e e 3 3 4.8 5.0 ma powerdown dissipation (v ih for logic levels must be 3.0 v) pdi = v ss fst and fsr = v ss , pdi = v dd e e 0.002 0.01 0.1 0.2 ma digital levels (v dd = + 5 v 10%, v ss = 0 v, t a = 40 to + 85 c) characteristics symbol min max unit input low voltage v il e 0.6 v input high voltage v ih 2.4 e v output low voltage (dt pin, i ol = 2.5 ma) v ol e 0.4 v output high voltage (dt pin, i oh = 2.5 ma) v oh v dd 0.5 e v input low current (v ss v in v dd ) i il 10 + 10 m a input high current (v ss v in v dd ) i ih 10 + 10 m a output current in high impedance state (v ss dt v dd ) i oz 10 + 10 m a input capacitance of digital pins (except dt) c in e 10 pf input capacitance of dt pin when highz c out e 15 pf
MC145484 motorola 12 analog electrical characteristics (v dd = + 5 v 10%, v ss = 0 v, t a = 40 to + 85 c) characteristics min typ max unit input current ti+, ti e 0.1 1.0 m a input resistance to v ag (v ag 0.5 v v in v ag + 0.5 v) ti+, ti 10 e e m w input capacitance ti+, ti e e 10 pf input offset voltage of tg op amp ti+, ti e e 5 mv input common mode voltage range ti+, ti 1.2 v dd 2.0 v input common mode rejection ratio ti+, ti e 60 e db gain bandwidth product (10 khz) of tg op amp (r l 10 k w ) e 3000 e khz dc open loop gain of tg op amp (r l 10 k w ) e 95 e db equivalent input noise (cmessage) between ti+ and ti at tg e 30 e dbrnc output load capacitance for tg op amp 0 e 100 pf output voltage range for tg (r l = 10 k w to v ag ) (r l = 2 k w to v ag ) 0.5 1.0 e e v dd 0.5 v dd 1.0 v output current (0.5 v v out v dd 0.5 v) tg, ro 1.0 e e ma output load resistance to v ag tg, ro 2 e e k w output impedance (0 to 3.4 khz) ro e 1 e w output load capacitance ro 0 e 500 pf dc output offset voltage of or ro referenced to v ag e e 25 mv v ag output voltage referenced to v ss (no load) v dd /2 0.1 v dd /2 v dd /2 + 0.1 v v ag output current with 25 mv change in output voltage 2.0 10 e ma power supply rejection ratio transmit (0 to 100 khz @100 mvrms applied to v dd , receive cmessage weighting, all analog signals referenced to v ag pin) 50 50 80 75 e e dbc power drivers pi, po+, po input current (v ag 0.5 v pi v ag + 0.5 v) pi e 0.05 1.0 m a input resistance (v ag 0.5 v pi v ag + 0.5 v) pi 10 e e m w input offset voltage pi e e 20 mv output offset voltage of po+ relative to po (inverted unity gain for po) e e 50 mv output current (v ss + 0.7 v po+ or po v dd 0.7 v) 10 e e ma po+ or po output resistance (inverted unity gain for po) e 1 e w gain bandwidth product (10 khz, open loop for po) e 1000 e khz load capacitance (po+ or po to v ag , or po+ to po) 0 e 1000 pf gain of po+ relative to po (r l = 300 w , + 3 dbm0, 1 khz) 0.2 0 + 0.2 db total signal to distortion at po+ and po with a differential load of: 300 w 100 nf in series with 20 w 100 w 45 e e 60 40 40 e e e dbc power supply rejection ratio 0 to 4 khz (0 to 25 khz @ 100 mvrms applied to v dd . 4 to 25 khz po connected to pi. differential or measured referenced to v ag pin.) 40 e 55 40 e e db
MC145484 motorola 13 analog transmission performance (v dd = + 5 v 10%, v ss = 0 v, all analog signals referenced to v ag , 0 dbm0 = 0.775 vrms = + 0 dbm @ 600 w , fst = fsr = 8 khz, bclkt = mclk = 2.048 mhz synchronous operation, t a = 40 to + 85 c, unless otherwise noted) ch i i a/d d/a ui characteristics min typ max min typ max units peak single frequency tone amplitude without clipping t max e 1.575 e e 1.575 e vpk absolute gain (0 dbm0 @ 1.02 khz, t a = 25 c, v dd = 5.0 v) 0.25 e + 0.25 0.25 e + 0.25 db absolute gain variation with temperature 0 to + 70 c (referenced to 25 c) 40 to + 85 c e e e e 0.03 0.05 e e e e 0.03 0.05 db absolute gain variation with power supply (t a = 25 c) e e 0.03 e e 0.03 db gain vs level tone (mulaw, relative to 10 dbm0, 1.02 khz) + 3 to 40 dbm0 40 to 50 dbm0 50 to 55 dbm0 0.30 0.8 1.2 e e e + 0.20 + 0.40 + 0.80 0.20 0.40 0.80 e e e + 0.20 + 0.40 + 0.80 db gain vs level pseudo noise, ccitt g.712 10 to 40 dbm0 (alaw, relative to 10 dbm0) 40 to 50 dbm0 50 to 55 dbm0 0.25 0.60 1.00 e e e + 0.25 + 0.30 + 0.45 0.25 0.30 0.45 e e e + 0.25 + 0.30 + 0.45 db total distortion, 1.02 khz tone + 3 dbm0 (mulaw, cmessage weighting) 0 to 30 dbm0 40 dbm0 45 dbm0 34 36 30 25 e e e e e e e e 34 36 30 25 e e e e e e e e dbc total distortion, pseudo noise, ccitt g.714 (alaw) 3 dbm0 6 to 27 dbm0 34 dbm0 40 dbm0 50 dbm0 55 dbm0 30 36 34 29 19 14 e e e e e e e e e e e e 30 36 35 30 20 15 e e e e e e e e e e e e db idle channel noise (for endtoend and a/d, see note 1) (mulaw, cmessage weighted) (alaw, psophometric weighted) e e e e 17 69 e e e e 11 79 dbr nc0 dbm0p frequency response (relative to 1.02 khz @ 0 dbm0) 15 hz 50 hz 60 hz 165 hz 200 hz 300 to 3000 hz 3000 to 3200 hz 3300 hz 3400 hz 3600 hz 4000 hz 4600 hz to 100 khz e e e e 1.0 0.20 0.20 0.35 0.8 e e e e e e 3.0 e e e e e 3.0 e e 40 30 26 e 0.4 + 0.15 + 0.20 + 0.15 0 e 14 32 0.5 0.5 0.5 0.5 0.5 0.15 0.20 0.35 0.85 e e e e e e e e e e e e 3.0 e e 0 0 0 0 0 + 0.15 + 0.20 + 0.15 0 e 14 30 db inband spurious (1.02 khz @ 0 dbm0, transmit and receive) 300 to 3400 hz e e 48 e e 48 db outofband spurious at ro+ (300 to 3400 hz @ 0 dbm0 in) 4600 to 7600 hz 7600 to 8400 hz 8400 to 100,000 hz e e e e e e e e e e e e e e e 30 40 30 db idle channel noise selective (8 khz, input = v ag , 30 hz bandwidth) e e e e e 70 dbm0 absolute delay (1600 hz) e e 315 e e 205 m s group delay referenced to 1600 hz 500 to 600 hz 600 to 800 hz 800 to 1000 hz 1000 to 1600 hz 1600 to 2600 hz 2600 to 2800 hz 2800 to 3000 hz e e e e e e e e e e e e e e 210 130 70 35 70 95 145 40 40 40 30 e e e e e e e e e e e e e e 85 110 175 m s crosstalk of 1020 hz @ 0 dbm0 from a/d or d/a (note 2) e e 75 e e 75 db intermodulation distortion of two frequencies of amplitudes ( 4 to 21 dbm0 from the range 300 to 3400 hz) e e 41 e e 41 db notes: 1. extrapolated from a 1020 hz @ 50 dbm0 distortion measurement to correct for encoder enhancement. 2. selectively measured while stimulated with 2667 hz @ 50 dbm0.
MC145484 motorola 14 digital switching characteristics, long frame sync and short frame sync (v dd = + 5 v 10%, v ss = 0 v, all digital signals referenced to v ss , t a = 40 to + 85 c, c l = 150 pf, unless otherwise noted) ref. no. characteristics min typ max unit 1 master clock frequency for mclk e e e e e e e 256 512 1536 1544 2048 2560 4096 e e e e e e e khz 1 mclk duty cycle for 256 khz operation 45 e 55 % 2 minimum pulse width high for mclk (frequencies of 512 khz or greater) 50 e e ns 3 minimum pulse width low for mclk (frequencies of 512 khz or greater) 50 e e ns 4 rise time for all digital signals e e 50 ns 5 fall time for all digital signals e e 50 ns 6 setup time from mclk low to fst high 50 e e ns 7 setup time from fst high to mclk low 50 e e ns 8 bit clock data rate for bclkt or bclkr 64 e 4096 khz 9 minimum pulse width high for bclkt or bclkr 50 e e ns 10 minimum pulse width low for bclkt or bclkr 50 e e ns 11 hold time from bclkt (bclkr) low to fst (fsr) high 20 e e ns 12 setup time for fst (fsr) high to bclkt (bclkr) low 80 e e ns 13 setup time from dr valid to bclkr low 0 e e ns 14 hold time from bclkr low to dr invalid 50 e e ns long frame specific timing 15 hold time from 2nd period of bclkt (bclkr) low to fst (fsr) low 50 e e ns 16 delay time from fst or bclkt, whichever is later, to dt for valid msb data e e 60 ns 17 delay time from bclkt high to dt for valid chord and step bit data e e 60 ns 18 delay time from the later of the 8th bclkt falling edge, or the falling edge of fst to dt output high impedance 10 e 60 ns 19 minimum pulse width low for fst or fsr 50 e e ns short frame specific timing 20 hold time from bclkt (bclkr) low to fst (fsr) low 50 e e ns 21 setup time from fst (fsr) low to msb period of bclkt (bclkr) low 50 e e ns 22 delay time from bclkt high to dt data valid 10 e 60 ns 23 delay time from the 8th bclkt low to dt output high impedance 10 e 60 ns
MC145484 motorola 15 mclk dt fst bclkt 7 11 15 16 3 17 4 8 9 10 18 18 16 12 6 2 1 5 bclkr dr fsr msb ch1 ch2 ch3 st1 st2 st3 lsb msb ch1 ch2 ch3 st1 st2 st3 lsb 14 13 8 9 10 123456789 123456789 15 12 11 figure 3. long frame sync timing
MC145484 motorola 16 mclk dt fst bclkt 7 12 3 22 4 8 9 10 23 22 11 6 2 1 5 bclkr dr fsr msb ch1 ch2 ch3 st1 st2 st3 lsb msb ch1 ch2 ch3 st1 st2 st3 lsb 14 13 8 9 10 123456789 123456789 12 11 20 21 20 21 figure 4. short frame sync timing
MC145484 motorola 17 digital switching characteristics for idl mode (v dd = 5.0 v 10%, t a = 40 to + 85 c, c l = 150 pf, see figure 5 and note 1) ref. no. characteristics min max unit 31 time between successive idl syncs note 2 32 hold time of idl sync after falling edge of idl clk 20 e ns 33 setup time of idl sync before falling edge idl clk 60 e ns 34 idl clock frequency 256 4096 khz 35 idl clock pulse width high 50 e ns 36 idl clock pulse width low 50 e ns 37 data valid on idl rx before falling edge of idl clk 20 e ns 38 data valid on idl rx after falling edge of idl clk 75 e ns 39 falling edge of idl clk to highz on idl tx 10 50 ns 40 rising edge of idl clk to lowz and data valid on idl tx 10 60 ns 41 rising edge of idl clk to data valid on idl tx e 50 ns notes: 1. measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level. 2. in idl mode, both transmit and receive 8bit pcm words are accessed during the b1 channel, or both transmit and receive 8bit pcm words are accessed during the b2 channel as shown in figure 5. idl accesses must occur at a rate of 8 khz (125 m s interval). ch1 msb idl tx (dt) lsb st3 st2 st1 ch3 ch2 ch1 msb lsb st3 st2 st1 ch3 ch2 ch1 msb lsb st3 st2 st1 ch3 ch2 ch1 msb lsb st3 st2 st1 ch3 idl rx (dr) idl clock (bclkt) idle sync (fst) 2 1 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 31 32 33 32 34 35 40 41 36 39 40 41 39 37 37 38 38 ch2 figure 5. idl interface timing
MC145484 motorola 18 digital switching characteristics for gci mode (v dd = 5.0 v 10%, t a = 40 to + 85 c, c l = 150 pf, see figure 6 and note 1) ref. no. characteristics min max unit 42 time between successive fsc pulses note 2 43 dcl clock frequency 512 6176 khz 44 dcl clock pulse width high 50 e ns 45 dcl clock pulse width low 50 e ns 46 hold time of fsc after falling edge of dcl 20 e ns 47 setup time of fsc to dcl falling edge 60 e ns 48 rising edge of dcl (after rising edge of fsc) to low impedance and valid data of d out e 60 ns 49 rising edge of fsc (while dcl is high) to low impedance and valid data of d out e 60 ns 50 rising edge of dcl to valid data on d out e 60 ns 51 second dcl falling edge during lsb to high impedance of d out 10 50 ns 52 setup time of d in before rising edge of dcl 20 e ns 53 hold time of d in after dcl rising edge e 60 ns notes: 1. measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level. 2. in gci mode, both transmit and receive 8bit pcm words are accessed during the b1 channel, or both transmit and receive 8bit pcm words are accessed during the b2 channel as shown in figure 6. gci accesses must occur at a rate of 8 khz (125 m s interval). 31 fsc (fst) 12 11 10 9 d in (dr) ch1 msb ch1 msb d out (dt) dcl (bclkt) 5 4 3 2 1 1 34 33 32 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 16 14 13 8 7 6 5 4 3 2 lsb st3 st2 st1 ch3 ch2 ch1 msb lsb st3 st2 st1 ch3 ch2 ch1 msb lsb st3 st2 st1 ch3 ch2 ch1 msb lsb st3 st2 st1 ch3 ch2 ch1 d in (dr) d out (dt) dcl (bclkt) fsc (fst) 46 46 47 44 43 45 49 48 52 53 52 53 52 53 msb 49 50 51 48 50 51 42 figure 6. gci interface timing
MC145484 motorola 19 pcm in 2.048 mhz pcm out 8 khz + 5 v 1.0 m f audio out + 5 v + 0.1 m f 0.01 m f 10 k w analog in pdi ro pi po po+ bclkr dr fsr v dd v ag ref mu/a mclk bclkt dt fst tg ti ti+ v ag v ss 20 19 18 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 9 10 k w 10 k w 10 k w 1.0 m f 0.1 m f 20 k 20 k figure 7. MC145484 test circuit e signals referenced to v ag pin + 68 m f pcm in 2.048 mhz pcm out 8 khz + 5 v 1.0 m f r l 2 k w audio out + 5 v 0.1 m f 0.01 m f 10 k w 10 k w 10 k w 10 k w analog in 20 19 18 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 9 10 k w 1.0 m f r l 150 w audio out pdi ro pi po po+ bclkr dr fsr v dd v ag ref mu/a mclk bclkt dt fst tg ti ti+ v ag v ss 20 k 0.1 m f 20 k figure 8. MC145484 test circuit e signals referenced to v ss
MC145484 motorola 20 8 khz 2.048 mhz 256 8 9 7 6 5 4 3 2 1 mc74hc4060 1/2 mc74hc73 1/2 mc74hc73 0.1 m f 10 m w 18 pf 18 pf 2.048 mhz (fst, fsr) (bclkt, bclkr, mclk) 8 khz 2.048 mhz r osc out 2 osc out 1 osc in gnd v cc q4 q8 + 5 v v cc gnd + 5 v q k j r q q k j + 5 v 300 w q r figure 9. long frame sync clock circuit for 2.048 mhz sidetone 420 pf 420 pf rec mic 68 m f +5 v pcm in 2.048 mhz pcm out 8 khz + 5 v 1.0 m f + 5 v 0.1 m f 0.01 m f 75 k w 1 k w 75 k w pdi ro pi po po+ bclkr dr fsr v dd v ag ref mu/a mclk bclkt dt fst tg ti ti+ v ag v ss 20 19 18 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 9 1.0 m f 1 k w 1 k w 1 k w 0.1 m f figure 10. MC145484 analog interface to handset
MC145484 motorola 21 b1 0 v b2 + 5 v r0 = 600 w r0 n = 1 n = 1 ring tip d in dcl 4.096 mhz d out fsc 8 khz + 5 v 1.0 m f + 5 v 0.1 m f 10 k w 20 19 18 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 9 0.1 m f 10 k w mu/a mclk bclkt dt fst tg ti ti+ v ag v ss pdi ro pi po po+ bclkr dr fsr v dd v ag ref 10 k w 10 k w 0.1 m f figure 11. MC145484 transformer interface to 600 w telephone line with gci clocking 48 v n = 0.5 r0 = 600 w n = 0.5 ring tip 1/4 r0 pcm in 2.048 mhz pcm out 8 khz 1.0 m f + 5 v n = 0.5 10 k w pdi ro pi po po+ bclkr dr fsr v dd v ag ref mu/a mclk bclkt dt fst tg ti ti+ v ag v ss 20 19 18 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 9 10 k w 0.1 m f 20 k w + 5 v 0.1 m f 0.1 m f 10 k w figure 12. MC145484 stepup transformer interface to 600 w telephone line
MC145484 motorola 22 mc33120/1 v dd pdi st1 v dg v ag rfo 12 13 14 9 10 8 11 rxi 15 txo v cc ep rsi bp cn vee notes: 1. component values can be adjusted as needed for desired transmit and receive gain, terminating impedance, and transhybrid loss. 2. + 5 v line should be clean and free of noise. 3. keep digital signal lines away from analog signal lines to keep noise from coupling into the analog sections. 4. see data sheets for additional information. cf 7 vqb 6 cp tsi bn en 20 19 18 17 16 5 4 3 2 1 mjd253 tip 1k, 2% 9.1 k 9.1 k 1k, 2% 100 w vee 0.01 m f ring mjd243 100 w vee 0.01 m f 0.1 m f battery voltage ( 24 to 48 v) MC145484 v ag ti+ ti mu/a v ss mclk 19 18 17 16 14 15 11 fst 20 tg v ag ref ro po+ pi fsr bclkr dt 13 bclkt 12 po v dd pdi dr 1 2 3 4 5 6 7 10 8 9 + 5 v 0.1 m f 4.7 m f 300 w 20 w 10 m f 1 m f 600 w 15.8 k 20.3 k 10 k 30.6 k 4.7 k 1 m f 0.005 m f 600 w 1 m f analog/ digital ground 0.1 m f 10 k 10 k 4.7 m f + 5 v 0.1 m f + 5 v pcm in 8 khz pcm out 2.048 mhz 31.6 k 31.6 k 6.2 k 1 m f 0.01 m f mc145436adw d4 d8 dv atb x in 15 14 13 12 10 11 x out 16 nc d2 d1 nc enb x en gnd 9 v dd gt a in 1 2 3 4 5 6 7 8 to mcu 1 m w 3.58 mhz 0.1 m f nc + 5 v 0.1 m f nc nc + 1 figure 13. pots line interface circuit using MC145484, mc33120/21, and mc145436a
MC145484 motorola 23 table 3. mulaw encodedecode characteristics chord number step decision decode number of steps size levels sign chord chord chord step step step step levels normalized encode normalized 12345678 digital code 8159 1 0 0 0 0 0 0 0 8031 7903 8 16 256 4319 1 0 0 0 1 1 1 1 4191 4063 7 16 128 2143 1 0 0 1 1 1 1 1 2079 2015 6 16 64 1055 1 0 1 0 1 1 1 1 1023 991 51632511 1 0 1 1 1 1 1 1 495 479 4 16 16 239 1 1 0 0 1 1 1 1 231 223 3 16 8 103 11011111 99 95 2164 35 11101111 33 31 1152 3 11111110 2 1 11 11111111 0 0 notes: 1. characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. digital code includes inversion of all magnitude bits.
MC145484 motorola 24 table 4. alaw encodedecode characteristics chord number step decision decode number of steps size levels sign chord chord chord step step step step levels normalized encode normalized 12345678 digital code 4096 1 0 1 0 1 0 1 0 4032 3968 7 16 128 2176 1 0 1 0 0 1 0 1 2112 2048 6 16 64 1088 1 0 1 1 0 1 0 1 1056 1024 5 16 32 544 1 0 0 0 0 1 0 1 528 512 4 16 16 272 1 0 0 1 0 1 0 1 264 256 3 16 8 136 1 1 1 0 0 1 0 1 132 128 2164 68 11110101 66 64 1322 2 11010101 1 0 notes: 1. characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. digital code includes inversion of all even numbered bits.
MC145484 motorola 25 package dimensions dw suffix sog package case 751d04 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c t seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 sd suffix ssop case 940c02 20 11 10 1 h a b p r notes: 1. controlling dimension: millimeter. 2. dimensions and tolerances per ansi y14.5m, 1982. 3. dimensions a and b do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15mm per side. 4. dimension is the length of terminal for soldering to a substrate. 5. terminal positions are shown for reference only. 6. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the lead width dimension. dim min max min max inches millimeters a 7.10 7.30 0.280 0.287 b 5.20 5.38 0.205 0.212 c 1.75 1.99 0.069 0.078 d 0.25 0.38 0.010 0.015 f 0.65 1.00 0.026 0.039 g 0.65 bsc 0.026 bsc h 0.59 0.75 0.023 0.030 j 0.10 0.20 0.004 0.008 l 7.65 7.90 0.301 0.311 m 0 8 0 8 n 0.05 0.21 0.002 0.008 g d s p m 0.120 (0.005) t 0.076 (0.003) n c m r m 0.25 (0.010) l j f m note 4
MC145484 motorola 26 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 5405, denver, colorado 80217. 3036752140 or 18004412447 3142 tatsumi kotoku, tokyo 135, japan. 81335218315 mfax ? : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 internet : http://www.mot.com/sps/ MC145484/d ?

▲Up To Search▲

Price & Availability of MC145484

	To Download MC145484 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .